Review Guidelines for Field-Programmable Gate Arrays in Nuclear Power Plant Safety Systems (NUREG/CR-7006, ORNL/TM-2009/20)

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Publication Information

Manuscript Completed: October 2009
Date Published: February 2010

Prepared by:
M. Bobrek¹, D. Bouldin², D.E. Holcomb¹, S.M. Killough¹
S.F. Smith¹, C. Ward¹, and R.T. Wood¹

¹Oak Ridge National Laboratory
P.O. Box 2008
Oak Ridge, TN 37831-6010

²University of Tennessee
419 Ferris Hall, 1508 Middle Drive
Knoxville, TN 37996-5483

M.E. Waterman, NRC Project Manager

NRC Job Code N6351

Office of Nuclear Regulatory Research
U.S. Nuclear Regulatory Commission
Washington DC 20555-0001

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Abstract

This report is a compilation of safe field-programmable gate array (FPGA) design practices that can be used by NRC staff as guidance for reviewing FPGA-based safety systems in nuclear power plants. It can also serve as a basis for development of specific activities that will support the licensing process such as FPGA-specific review procedures and acceptance criteria. The report follows on the investigation of existing regulatory documents and standards related to design and review of safety-related FPGA systems. Since the existing regulatory documents are not specific about FPGA design practices, this report also serves as the complement to the standards that cover general issues related to digital and software safety systems in nuclear power plants.

FPGA design practices are classified into three major groups—FPGA hardware design practices, FPGA design entry methods, and FPGA design methodologies. Within these major groups, design practices are further classified according to four top-level attributes—reliability, robustness, traceability, and maintainability according to the framework used in NUREG/CR-6463.

The report focuses on listing and describing FPGA design practices that are potentially unsafe as well as on suggesting which ones are acceptable for safety-critical designs. Additionally, the report outlines a design life cycle that could be used by the designers and the reviewers for FPGA-based safety systems.